udp_send1

所属分类VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:52KB
下载次数:40
上传日期:2016-03-10 15:23:29
上 传 者icebin
说明:  基于FPGA的UDP硬件协议栈, 全部用SystemVerilog写的,不需CPU参与,包括独立的MAC模块。 支持外部phy的配置,支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data_valid, input gtx_clk, output logic tx_en
(UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows: input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data)

文件列表:[举报垃圾]
udp_send
........\src
........\...\data_gen.sv,2324,2016-02-14
........\...\data_source.sv,6251,2016-02-19
........\...\dp_ram.v,470,2016-02-13
........\...\eth_fsm.sv,23254,2016-02-25
........\...\headers_ram.v,3865,2016-02-14
........\...\icmp_ram_int.v,1569,2016-02-18
........\...\mac_config.sv,6214,2016-02-14
........\...\mac_rx_path.sv,16708,2016-02-14
........\...\mac_tx_path.sv,8962,2016-02-18
........\...\rst_ctrl.v,423,2015-04-24
........\...\rx_ram.sv,3625,2016-02-25
........\...\rx_ram_int.v,1570,2016-02-25
........\...\simple_mac
........\...\..........\CRC32_D8_AAL5.v,2226,2015-04-13
........\...\..........\CRC32_D8_TX.v,2112,2015-04-24
........\...\..........\mac_fifo_rx.v,1574,2016-02-14
........\...\..........\mac_fifo_rx_size.v,1576,2016-02-14
........\...\..........\mac_fifo_tx.v,1574,2016-02-14
........\...\..........\mac_fifo_tx_size.v,1576,2016-02-14
........\...\..........\rx_header_align32.sv,1943,2016-02-14
........\...\..........\simple_mac_bus_arb.sv,1565,2016-02-14
........\...\..........\simple_mac_phy_mdio.sv,8367,2016-02-14
........\...\..........\simple_mac_regs.sv,2496,2016-02-14
........\...\..........\simple_mac_rx_gmii.sv,2547,2016-02-14
........\...\..........\simple_mac_rx_path.sv,10196,2016-02-14
........\...\..........\simple_mac_rx_rgmii.sv,2866,2016-02-14
........\...\..........\simple_mac_top.sv,5594,2016-02-14
........\...\..........\simple_mac_tx_gmii.sv,1728,2016-02-14
........\...\..........\simple_mac_tx_path.sv,8376,2016-02-14
........\...\..........\simple_mac_tx_rgmii.sv,1767,2016-02-14
........\...\..........\tx_header_align32.sv,1927,2016-02-14
........\...\tcpip_hw.sv,5379,2016-02-18
........\...\tcpip_hw1.sv,5379,2016-02-18
........\...\tcpip_hw_defines.sv,70,2016-02-13
........\...\tcpip_hw_ifs.sv,4690,2016-02-25
........\...\tcpip_hw_top.v,2883,2016-03-08
........\...\tcpip_hw_top.v.1,2823,2016-02-18
........\...\tcp_send.sdc,2095,2016-02-13
........\...\tx_ram.sv,6940,2016-02-25
........\...\tx_ram_int.v,1574,2016-02-25
........\...\type_defs.pkg.sv,6564,2016-03-08
........\...\vendor
........\...\......\altera
........\...\......\......\sync_fifo.v,7207,2016-02-11
........\...\......\......\sync_fifo_bb.v,6073,2016-02-11
........\tcpip_hw.qpf,1281,2015-02-17
........\tcpip_hw.qsf,9393,2016-03-08

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